+1 vote
I would like to know the difference in terms of hardware and software?
asked Dec 7, 2015 in Electro-Communication by srmayur22 | 3,858 views

2 Answers

+2 votes
Verilog and vhdl are Hardware Description language that are used to write programs for electronic chips .

These language are used in electronic devices that do not share computers basics architecture .
Vhdl is the older of the two and is based on Ada and Pascal , thus inheriting characteristics from both languages . 
Verilog is relatively recent and follows the coding methods of c programming language.
VHDL is strongly typed language and scripts that are not strongly typed are unable compile . A strongly typed language like vhdl does not allow the intermixing or operation of variables with different classes . verilog uses week typing ,which is the opposite of strongly typed language. 

Another difference is the case sensitivity.Verilog is case sensitive, and would not recognise a variable if the case used is not consistent with what it was previously . on the other hand, VHDL is not case sensitive .

1. Verilog is based on C , while VHDL is based on Pascal and Ada .
2. Unlike Verilog, VHDL is strongly typed
3. Unlike Vhdl , Verilog is case sensitive .
4. Verilog is easier to learn compared to VHDL .
5. Verilog has very simple data types , while VHDL allows users to create more complex data types .
6. Verilog lacks the library management ,like that of VHDL .
answered Jan 10, 2016 by KIRAN
edited Mar 31, 2017 by ppk
any example on syntax of the both ? +1
–1 vote

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, Verilog, and SystemVerilog. They differ from software programming languages because they include a means of describing propagation time and signal strengths. These days, it would be impossible to design a complex system on a chip (SoC) for a mobile device or any other consumer electronics product without an HDL.

Each of the three HDLs has its own distinct style. VHDL and Verilog implement register-transfer-level (RTL) abstractions. When they were first introduced in the late 1980s, they were considered breakthrough technologies because they enabled engineers to work at a higher level of abstraction with RTL simulators. Previously, engineers simulated their designs at the schematic or gate level.SystemVerilog was developed to provide an evolutionary path from VHDL and Verilog to support the complexities of SoC designs. It’s a bit of a hybrid—the language combines HDLs and a hardware verification language using extensions to Verilog, plus it takes an object-oriented programming approach. SystemVerilog includes capabilities for testbench development and assertion-based formal verification.

answered Dec 7, 2015 by anand.amrit27