Verilog and vhdl are Hardware Description language that are used to write programs for electronic chips .These language are used in electronic devices that do not share computers basics architecture .
Vhdl is the older of the two and is based on Ada and Pascal , thus inheriting characteristics from both languages .
Verilog is relatively recent and follows the coding methods of c programming language.
VHDL is strongly typed language and scripts that are not strongly typed are unable compile . A strongly typed language like vhdl does not allow the intermixing or operation of variables with different classes . verilog uses week typing ,which is the opposite of strongly typed language .Another difference is the case sensitivity.Verilog is case sensitive, and would not recognise a variable if the case used is not consistent with what it was previously . on the other hand, VHDL is not case sensitive .
1. Verilog is based on C , while VHDL is based on Pascal and Ada .
2. Unlike Verilog, VHDL is strongly typed
3. Unlike Vhdl , Verilog is case sensitive .
4. Verilog is easier to learn compared to VHDL .
5. Verilog has very simple data types , while VHDL allows users to create more complex data types .
6. Verilog lacks the library management ,like that of VHDL .